[ ] System Verilog |
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spice , pi-spice, mmsim, hspice .. ( , ). Spice . , , : , , ..
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. System Verilog shortreal ( float ) real. , . , .. reg, 0 1, , , , .
, wire, , . , System Verilog . , , , , . , ncsim, var, real wire. :
real a;
var real b;
assign a = in1+in2; //
assign b = in1+in2; // , b in1+in2verilog . , , , . assign , .
var, :
real b;
always @( * ) // always in1 in2
b <= in1+in2;, .
verilog
$itor() // integer to real
$rtoi() // real to integer
$bitstoreal() //reg [ : ] to real
$realtobits() // real to reg [ : ] , real , , . , - , , .
reg [7:0] code;
int a;
real voltage;
always @( * )
begin
a = {{24{code[7]}}, code[7:0]}; // int
voltage = a;
endmodule amp(input var real in, output real out);
parameter k = 10; //
parameter seed = 60;
parameter noise_power = -20; // dB
real noise;
always @(*)
begin
noise = $sqrt(10**(noise_power/10))* $itor($dist_normal(seed, 0 , 100_000))/100_000;
out = in * k + noise;
end
endmodule`timescale 1ns / 1ps
module DAC(input signed [7:0] DAC_code, output real out);
parameter fs = 10e-9;
parameter ffilt = fs/64; //
parameter CUTOFF = 100e6; //
parameter a = ffilt/(ffilt+(1/(2*3.141592* CUTOFF)));
real DAC_out;
//
always @( * )
DAC_out <= $bitstoint(DAC_code[7:0]);
// 1
always #(0.5*ffilt)
out <= a* DAC_out + (1-a)*out;
endmodulemodule ADC (input real in, input clk, output reg [7:0] ADC_code)
real adc_tf[0:255];
real min_dist;
int i,j;
int dnl_file;
initial
begin
dnl_file=$fopen("DNL_file","r");
if(dnl_file==0)
$stop;
for(i=0;i<256;i=i+1)
$fscanf(dnl_file, "%f;", adc_tf[i]);//
end
always @(posedge clk)
begin
min_dist = 10;
for(j=0;j<256; j=j+1) //
if($abs(in- adc_tf[j]) < min_dist)
begin
min_dist = delta_abs;
ADC_code[7:0]=j;
end
end
endmodulemodule MPLL (input en, input [5:0]phase, output clk_out);
parameter REFERENCE_CLOCK_PERIOD=10e-6;
parameter PHASES_NUMBER=64;
reg [PHASES_NUMBER-1:0]PLL_phase=64'h00000000_FFFFFFFF; //
always #(REFERENCE_CLOCK_PERIOD/PHASES_NUMBER)
if(en===1)
PLL_phase[PHASES_NUMBER-1:0] <= {PLL_phase[PHASES_NUMBER-2:0], PLL_phase[PHASES_NUMBER-1]}; //
assign clk_out = PLL_phase[phase]; //
endmodule, , spice System Verilog.
, , , . Verilog , , , .
SystemVerilog Direct Programming Interface (DPI). .. , , .
, import.
import "DPI-C" function int some_funct(input string file_name, input int in, output real out);
Verilog , , :
always @(posedge clk)
res1 <= some_funct (file.name, in1, out1); .
,
#include
typedef struct
{
//work specific
double in; //
double out; //
//thread specific
char processing; //
pthread_mutex_t mutex;
pthread_cond_t cond_start;
pthread_cond_t cond_finish;
void *next_th_params;
pthread_t tid;
}th_params;
static th_params th_pool[POOL_SIZE];:
void* worker_thread(void *x_void_ptr)
{
th_params *x_ptr = (th_params *)x_void_ptr;
while(1) //
{
//
pthread_mutex_lock (&x_ptr->mutex); //
x_ptr->processing = 0; //,
pthread_cond_signal(&x_ptr->cond_finish); // ,
while(x_ptr->processing == 0)
pthread_cond_wait(&x_ptr->cond_start, &x_ptr->mutex); //
x_ptr->processing = 1; // -
pthread_mutex_unlock(&x_ptr->mutex); //
// - , SSE2
}
}
void init(th_params *tp)
{
int i=0;
for(;i<12;i++)
{
pthread_attr_t attr;
pthread_attr_init(&attr);
pthread_attr_setdetachstate(&attr, PTHREAD_CREATE_DETACHED);
pthread_create(th_pool->tid, &attr, &worker_thread, tp);
}
}, ( Verilog )
int ch(double in, double *out)
{
int i;
for(i=0;i<12;i+=1)
{
//
pthread_mutex_lock(&th_pool[i].mutex); //
while(th_pool[i].processing == 1)
pthread_cond_wait(&th_pool[i].cond_finish, &th_pool[i].mutex); //
pthread_mutex_unlock(&th_pool[i].mutex); //
}
// Verilog
for(i=0;i<12;i+=1)
out[i] = th_pool[i].out;
for(i=0;i<12;i+=1)
{
pthread_mutex_lock (&th_pool[i].mutex); //
th_pool[i].in = in; //
th_pool[i].processing = 1; //
pthread_cond_signal (&th_pool[i].cond_start); // ,
pthread_mutex_unlock (&th_pool[i].mutex); //
}
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